Power conversion integrated circuit and method for programming

ABSTRACT

A single input pin ( 48 ) provides multi-functional features for programming a power supply ( 10 ). By connecting the appropriate interface circuit ( 92, 100,  or  112 ) to the single input pin ( 48 ), the power supply ( 10 ) is programmed for specific behaviors during power up and toggling of an on/off switch ( 96, 108 ). In one mode of operation a light emitting diode ( 106 ) in the interface circuit ( 100 ) is optically coupled to a microprocessor for signaling the closure of the on/off switch ( 108 ), allowing the microprocessor to control the power supply ( 10 ) through an opto-coupler ( 102 ). In another mode of operation, the single on/off switch ( 96 ) controls the power supply ( 10 ). In yet another mode of operation, Zener diode ( 118 ) in the interface circuit ( 112 ) controls the power supply ( 10 ) during brown-out and black-out conditions.

CROSS-REFERENCE TO RELATED APPLICATIONS

More than one reissue application has been filed for the reissue of U.S.Pat. No. 5,859,768. The reissue applications are application Ser. Nos.10/946,611 and 09/709,893, now U.S. Pat. No. RE39,933, all of which aredivisional reissues of U.S. Pat. No. 5,859,768.

BACKGROUND OF THE INVENTION

The present invention relates, in general, to integrated circuits and,more particularly, to a power conversion integrated circuit.

A power supply is controlled to be either on or off by a mechanicalswitch or a relay. Typically, additional discrete components that areexternal to the integrated circuit adapt the power supply for use inapplications such as cable converters for television sets, computermonitors, video cassette recorders (VCRs), battery chargers for portablecommunications devices, computer printers, and other electronic systems.

Depending on the particular application, the on/off circuitry of a powersupply control circuit includes components such as opto-couplers,latches, resistors, and capacitors. Monolithic circuit integrationminimizes the number of components external to the integrated circuitand reduces the cost of power supplies. The number and types of externalcomponents along with the cost of the integrated circuit package providefunctionality that differentiates among different power supplies.Typically, a switching regulator without on/off circuitry ismanufactured in a three pin package. A drawback of these three pinpackage configurations is that they offer limited functionality withinthe package.

Accordingly, it would be advantageous to have an inexpensive integratedpower supply controller that is capable of operating with many differentpower supplies. It would be of further advantage for the power supplycontroller to have a minimal number of discrete external components forcontrolling the power supply on/off switch circuitry.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a power supply in accordance with anembodiment of the present invention;

FIG. 2 is a schematic diagram of a state circuit for use in the powersupply of FIG. 1;

FIG. 3 is a schematic diagram of an interface switch circuit for usewith the state circuit of FIG. 1 in accordance with another embodimentof the present invention;

FIG. 4 is a schematic diagram of a microprocessor interface switchcircuit for use with the state circuit of FIG. 1 in accordance with yetanother embodiment of the present invention; and

FIG. 5 is a schematic diagram of a brown-out interface circuit for usewith the state circuit of FIG. 1 in accordance with yet anotherembodiment of the present invention.

DETAILED DESCRIPTION OF THE DRAWINGS

Generally, the present invention provides a circuit with at least fourmodes of operation for controlling the on/off features of a powersupply. By connecting an appropriate interface circuit to a state inputpin, the power supply is programmed for specific behaviors when power isapplied or when the interface circuitry is activated. Thus, themultifunctionality provided by a state circuit that is integrated with acontrol circuit is a cost effective solution for controlling the powersupply.

FIG. 1 is a block diagram of a power supply 10 in accordance with thepresent invention. Power supply 10 includes a full-wave bridge rectifier12, capacitors 14, 24, and 34, diodes 22 and 32, a transformer 16, acompensated error amplifier 42, and a power converter circuit 44. Inparticular, full-wave bridge rectifier 12 has a ground connection, apair of inputs for receiving a line voltage, e.g., 110 volts alternatingcurrent (VAC), 220 volts VAC, etc. An output of full-wave bridgerectifier 12 supplies a rectified output signal that is filtered byfilter capacitor 14. Filter capacitor 14 has a terminal connected to theoutput of full-wave bridge rectifier 12 and a terminal connected to apower supply potential such as, for example, ground.

Transformer 16 has a primary side or winding 18 having two terminals, asecondary winding 20 having two terminals, and a secondary winding 30having two terminals. In particular, one terminal of primary winding 18is connected to the output of full-wave bridge rectifier 12, and theother terminal of primary winding 18 is connected to a switch output pin40 of power converter circuit 44.

Secondary winding 20 has a first terminal connected to an anode of adiode 22. A cathode of diode 22 is commonly connected to a firstterminal of capacitor 24 and to a terminal 26. The second terminal ofcapacitor 24 is commonly connected to the second terminal of secondarywinding 20 and to a terminal 28. Compensated error amplifier 42 has aninput connected to terminal 26, an input connected to terminal 28, andan output connected to feedback pin 46.

Secondary winding 30 has a first terminal connected to an anode of diode32. A cathode of diode 32 is commonly connected to a first terminal ofcapacitor 34 and to a bias pin 36 of power converter circuit 44. Thesecond terminal of capacitor 34 is commonly connected to the secondterminal of secondary winding 30 and to a potential such as, forexample, ground.

Power converter circuit 44 is a switched mode power supply integratedcircuit or a power conversion integrated circuit having five electricalconnection terminals: (1) a bias pin 36, (2) a ground pin 38, (3) afeedback pin 46, (4) a state pin 48, and (5) a switch output pin 40.Power converter circuit 44 is a semiconductor chip that includes a statecircuit 50, a control circuit 52 having an internal regulator, and atransistor 54. State circuit 50 has an input connected to bias pin 36and another input coupled to state pin 48 of power converter circuit 44.Another input of state circuit 50 is connected to an output of controlcircuit 52 and receives a logic under-voltage control signal (LOGIC).Another input of state circuit 50 receives an analog under-voltagecontrol signal (ANALOG) and is connected to a second output of controlcircuit 52. An output of state circuit 50 provides a signal MODE and isconnected to a control input of control circuit 52. Control circuit 52has an input connected to bias pin 36 and another input connected tofeedback pin 46 of power converter circuit 44. An output of controlcircuit 52 is connected to a gate of transistor 54. Both state circuit50 and control circuit 52 are connected to ground pin 38. A drain oftransistor 54 is connected to switch output pin 40 and a source isconnected to ground pin 38. As those skilled in the art are aware, agate of a transistor serves as a control terminal and the drain andsource of a transistor serve as current conduction terminals. It shouldbe noted that transistor 54 can be an insulated gate bipolar transistor(IGBT), a bipolar transistor, etc.

In operation, the line voltage, e.g., 110 VAC, is rectified by full-wavebridge rectifier 12 and filtered by capacitor 14. Secondary winding 20provides a signal that is used to supply the operating power toelectronic systems such as cable converters, computer monitors, videocassette recorders (VCRs), battery chargers, computer printers, etc.Compensated error amplifier 42 provides a feedback signal to powerconverter circuit 44 that is proportional to the DC output signal. Theoutput of compensated error amplifier 42 may be optically, electrically,magnetically, mechanically, or other means coupled to feedback pin 46 ofpower converter circuit 44.

The feedback signal is used by control circuit 52 for altering the pulsewidth of the signal that is supplied to the control terminal oftransistor 54. Thus, compensated error amplifier 42 alters the pulsewidth of the output signal at switch output pin 40 in accordance withthe voltage developed across terminals 26 and 28. The variable pulsewidth modifies the current in transformer 16, thereby regulating thevoltage of the DC output signal. In addition, the bias voltage developedat bias pin 36 from secondary winding 30 can used as the operatingsupply voltage of state circuit 50 and control circuit 52. The biasvoltage developed at bias pin 36 can alternately be derived fromsecondary winding 20. It should be noted that compensated erroramplifier 42 can be replaced with a high gain comparator, or the like.

FIG. 2 is a schematic diagram of state circuit 50 in accordance with thepresent invention. State circuit 50 includes a reference generator 60, areset circuit 65, a positive detector circuit 76, a negative detectorcircuit 78, and a mode memory circuit 90. Positive detector circuit 76and negative detector circuit 78 are referred to as a comparatorcircuit. In particular, reference generator 60 includes resistors 62,64, 66, 68, 70, and 72, and a voltage clamp circuit 74. The firstterminals of resistors 62 and 64 are commonly connected to state pin 48which is connected to an input of state circuit 50. The second terminalof resistor 62 is connected to a power supply conductor which is coupledfor receiving a voltage such as, for example, V_(cc), and the secondterminal of resistor 64 is connected to a power supply conductor whichis coupled for receiving a reference voltage of, for example, ground.The first terminals of resistors 66 and 68 are commonly connected andform a node 67. The second terminal of resistor 66 is connected to thepower supply conductor which is coupled for receiving the referencevoltage of, for example, V_(cc). The second terminal of resistor 68 andthe first terminal of resistor 70 are commonly connected and form a node69. The second terminal of resistor 70 and the first terminal ofresistor 72 are commonly connected and form a node 71. The secondterminal of resistor 72 is connected to a power supply conductor whichis coupled for receiving a reference voltage of, for example, ground. Itshould be noted that the power supply conductor connected to ground isalso connected to the external ground reference or ground pin 38 ofpower converter circuit 44 (FIG. 1). Voltage clamp circuit 74 has aninput connected to node 69 and an output connected to state pin 48. Byway of example, voltage clamp circuit 74 is a PNP transistor 75 having abase terminal connected to the input of voltage clamp 74, an emitterterminal connected to the output of voltage clamp circuit 74, and acollector terminal connected to a potential of, for example, ground.

The resistors 62, 64, 66, 68, 70, and 72 of reference generator 60 (FIG.2) set reference voltages that determine the logic values of the signalsat the outputs of comparators 77 and 80. By way of example, resistor 62has a value of about 160 kilohms (KΩs), resistor 64 has a value of about115 KΩs, resistor 66 has a value of about 150 KΩs, resistor 68 has avalue of about 19 KΩs, resistor 70 has a value of about 58 KΩs, andresistor 72 has a value of about 55 KΩs. Resistors 62 and 64 form aresistor divider network that provides a voltage of about 2.4 volts atstate pin 48 when external components are not connected at that pin. Itshould be further noted that resistors 66, 68, 70, and 72 form anotherresistor divider network that provides voltages at nodes 67 and 71 ofabout 2.9 volts and about 1.1 volts, respectively. The referencevoltages described are for a V_(cc) of approximately 5.8 volts. Itshould be noted that reference generator 60 can be configured with othercombinations of resistors or alternately configured with combinations ofresistors and semiconductor devices.

Positive detector circuit 76 includes a comparator 77 having anon-inverting input connected to an input of positive detector circuit76, and thus to node 67 of reference generator 60. An inverting input ofcomparator 77 is connected to an input of positive detector circuit 76and thus to state pin 48 of reference generator 60. An output ofcomparator 77 is connected to an output of positive detector circuit 76.Negative detector circuit 78 includes a comparator 80 connected to apulse filter 82. Comparator 80 has a non-inverting input connected to aninput of negative detector circuit 78 and thus to node 71 of referencegenerator 60. An inverting input of comparator 80 is connected to aninput of negative detector circuit 78 and thus to state pin 48 ofreference generator 60. An output of comparator 80 is coupled to anoutput of negative detector circuit 78 through pulse filter 82.

Reset circuit 65 receives an input signal LOGIC UNDER-VOLTAGE and has anoutput connected to state pin 48.

Mode memory circuit 90 includes a two-input NAND gate 84, a logiccircuit 86, and a positive edge triggered toggle flip-flop 88. Inparticular, two-input NAND gate 84 has an input connected to the outputof positive detector circuit 76, the other input is coupled forreceiving the signal LOGIC UNDER-VOLTAGE. When the voltage V_(cc) beginsto ramp from a starting voltage of zero volts, the signal LOGICUNDER-VOLTAGE has an initial logic zero value that is switched to alogic one value at a predetermined voltage. By way of example, thepredetermined voltage is a voltage potential that is sufficiently highto allow logic circuitry to properly operate. In other words, the signalLOGIC UNDER-VOLTAGE has a logic one value when the voltage V_(cc) issufficiently above the predetermined voltage and a logic zero value whenbelow the predetermined voltage.

Logic circuit 86 has an input R coupled for receiving the signal LOGICUNDER-VOLTAGE, an input S connected to the output of negative detectorcircuit 78, and an enable input E coupled for receiving the signalANALOG UNDER-VOLTAGE. The signal ANALOG UNDER-VOLTAGE has a logic onevalue when the voltage V_(cc) is sufficiently high for transistors (notshown) such as, for example, the transistors in comparators 77 and 80,to operate in an analog mode. When the voltage V_(cc) is not high enoughfor transistors to operate in the analog mode the signal ANALOGUNDER-VOLTAGE has a logic zero value.

It should be noted that when a signal having a logic zero value isreceived at the input R of logic circuit 86, the output signal at outputQ of logic circuit 86 has a logic zero value. It should be further notedthat when a signal having a logic one value is received at the input Sof logic circuit 86, the output signal at output Q of logic circuit 86has a logic one value. Should logic circuit 86 receive both a signalhaving a logic zero value at the input R and a signal having a logic onevalue at the input S, the circuit responds to the signal received at theinput R. In other words, when both a set and a reset occur together, thereset function has precedence. It should be noted that the output Q canonly transition from a logic zero value to a logic one value when theenable input, i.e., the signal ANALOG UNDER-VOLTAGE, is a logic one.

Toggle flip-flop 88 has an input S connected to the output of NAND gate84, an input CLK connected to the output of logic circuit 86, and anoutput that also serves as the output of state circuit 50. It should benoted that the output signal of toggle flip-flop 88 can be set to alogic one value when the input S receives a logic one signal. Otherwise,the stored value of the output signal changes output state in responseto logic transitions at input CLK, i.e., the stored value is toggledwhen the input CLK transitions from a logic zero value to a logic onevalue. It should be noted that if the signal at the input CLKtransitions while the signal at input S is a logic one, then flip-flop88 responds to a logic one signal at input S and ignores the signal atthe input CLK.

In operation, the power supply conductor V_(cc) initially starts at avoltage of about zero volts and ramps to a higher voltage value,increasing in voltage to a voltage greater than 5.8 volts. As thevoltage V_(cc) begins to ramp from zero volts, the signals LOGICUNDER-VOLTAGE and ANALOG UNDER-VOLTAGE initially have logic zero values.The signal LOGIC UNDER-VOLTAGE is set to a logic one when the voltageV_(cc) exceeds about 3.5 volts. The signal ANALOG UNDER-VOLTAGE is setto a logic one value when the voltage V_(cc) exceeds about 4.8 volts.

In a first operating mode, no external components are connected to statepin 48. With the application of the line voltage, the voltage for V_(cc)increases from zero volts. The signal LOGIC UNDER-VOLTAGE has a logiczero value when the voltage V_(cc) is in the range of about 0 volts toabout 3.5 volts. The logic zero value for the signal LOGIC UNDER-VOLTAGEcauses both the output of logic circuit 86 to have a logic zero valueand the output of toggle flip-flop 88 to have a logic one value. Whenthe signal LOGIC UNDER-VOLTAGE is at a logic zero value, input state pin48 is pulled to ground through reset circuit 65. When the voltage V_(cc)increases above a voltage of about 3.5 volts the output of reset circuit65 becomes a high impedance output. With no external components, thevoltage at state pin 48 is determined by the values of resistors 62 and64. In this first mode of operation the voltage on state pin 48 isbetween the reference voltages at nodes 67 and 71, the signal at theoutput of comparator 77 has a logic one value, and the output ofcomparator 80 has a logic zero value. Thus, the signal MODE is a logicone and power supply 10 (FIG. 1) is on.

FIG. 3 is a schematic diagram of an interface switch circuit for usewith the state circuit of FIG. 1 in accordance with another embodimentof the present invention. In a second operating mode, switch interfacecircuit 92 is connected to state circuit 50 for controlling theoperation of power supply 10 (FIG. 1). Briefly referring to FIG. 3,switch interface circuit 92 includes a resistor 94, a push-button ormechanical switch 96, and a capacitor 98. In particular, a firstterminal of resistor 94 is connected to a first terminal of switch 96.The second terminal of resistor 94 is connected to a power supplyconductor that is coupled for receiving a voltage such as, for example,ground, and the second terminal of switch 96 is connected to a firstterminal of capacitor 98, forming node 48A. Node 48A is connected tostate pin 48 in this mode of operation. The second terminal of capacitor98 is connected to a power supply conductor such as, for example,ground.

The reference voltage or reference signal at node 67 is transmitted tothe non-inverting input of comparator 77 and the voltage at state pin 48is transmitted to the inverting input of comparator 77. If the voltageat state pin 48 is less than the reference voltage at node 67, theoutput of comparator 77 is a logic one value. On the other hand, if thevoltage at state pin 48 is greater than the reference voltage at node67, the output of comparator 77 is a logic zero value. The referencevoltage or reference signal at node 71 is transmitted to thenon-inverting input of comparator 80 and the voltage at state pin 48 istransmitted to the inverting input of comparator 80. If the voltage atstate pin 48 is greater than the reference voltage at node 71, theoutput of comparator 80 is a logic zero value. On the other hand, if thevoltage at state pin 48 is less than the reference voltage at node 71,the output of comparator 80 is a logic one value. Together, comparators77 and 80 determine whether the voltage at state pin 48 is between thereference voltages at nodes 67 and 71.

In the second mode of operation, switch 96 allows for manuallycontrolling whether power supply 10 (FIG. 1) is in an on-operating stateor an off-operating state. Initially, the signals LOGIC UNDER-VOLTAGEand ANALOG UNDER-VOLTAGE have logic zero values. The signal LOGICUNDER-VOLTAGE causes the output of logic circuit 86 to have a logic onevalue, and for state pin 48 to be grounded by reset circuit 65 anddischarge capacitor 98. The output of NAND gate 84 is a logic one valuethat sets the output of toggle flip-flop 88 to a logic one value.

With the application of the line voltage to full-wave bridge rectifier12, the voltage V_(cc) (see FIG. 2) is increased from the startingvoltage of zero volts. As the voltage for V_(cc) increases above about3.5 volts the signal LOGIC UNDER-VOLTAGE changes to a logic one value.In addition, the output of reset circuit 65 becomes high impedanceallowing capacitor 98 to charge. A further increase in the voltageV_(cc) above about 4.8 volts causes the signal ANALOG UNDER-VOLTAGE tobe set to a logic one value which enables logic circuit 86. The outputof comparator 80 being at a logic one value signifies that capacitor 98is at a value that is less than the voltage at node 71. The logic onevalue at the output of comparator 80 causes the output of logic circuit86 to transition from a logic zero value to a logic one value. When thelogic zero value at the CLK input transitions to a logic one value thepreviously stored value of toggle flip-flop 88 is toggled. Thus, theoutput signal MODE has a logic zero value and power supply 10 is in anoff state.

When switch 96 is closed, capacitor 98 is discharged through switch 96and resistor 94. The voltage at state pin 48 drops below the referencevoltage at node 71 causing comparator 80 to provide a logic one to inputS of logic circuit 86. The output of logic circuit 86 transitions to alogic one value causing toggle flip-flop 88 to change states such thatthe signal MODE is a logic one value and power supply 10 is in an onstate. With each closure of switch 96 the output of logic circuit 86transitions from a logic zero to a logic one causing the stored data intoggle flip-flop 88 to change state, provided that capacitor 98 wascharged above the reference voltage at node 71.

FIG. 4 is a schematic diagram of a microprocessor interface switchcircuit for use with the state circuit of FIG. 1 in accordance withanother embodiment of the present invention. In a third operating mode,a microprocessor interface switch circuit 100 (FIG. 4) is connected tostate circuit 50 (FIG. 2) for controlling the operation of power supply10 (FIG. 1). A first terminal of capacitor 110 and the collectorterminal of opto-coupler 102 are commonly connected, forming node 48B.Node 48B is connected to state pin 48 of state circuit 50. The secondterminal of capacitor 110 and the emitter terminal of opto-coupler 102are connected to a power supply conductor at a potential of, forexample, ground. The base terminal is coupled for receiving a codedlight signal. Resistor 104 has a terminal connected to state pin 48 andthe other terminal connected to a cathode of LED 106. An anode of LED106 is connected to a first terminal of switch 108. A second terminal ofswitch 108 is connected to a power supply conductor coupled forreceiving a voltage such as, for example, V_(cc). It should be notedthat switch 108 may be a push-button switch that is closed while thebutton is depressed, i.e., a momentary closure.

In the third mode of operation, state circuit 50 is powered on such thatthe signal MODE has a logic zero value. Capacitor 110 delays thecharging of state pin 48 so that the output of comparator 80 has a logicone value, which turns off power supply 10. The momentary closure ofswitch 108 causes LED 106 to emit light and transmit a signal to, forexample, a microprocessor (not shown). When switch 108 is closed, statepin 48 is pulled high through switch 108, LED 106, and resistor 104. Thevoltage at state pin 48 is clamped by voltage clamp circuit 74 such thatLED 106 is always forward biased and emitting light when switch 108 isclosed. When switch 108 is closed the output of comparator 77 becomes alogic zero value signifying that the voltage on state pin 48 is abovethe reference voltage established at node 67 by the resistor dividernetwork. The logic zero value sets the signal MODE to a logic one valuefor turning on power supply 10 (FIG. 1).

When the signal MODE is a logic one and power supply 10 is on, anothermomentary closure of switch 108 signals the microprocessor through lightemitted by LED 106 of a request to shut down power supply 10. Themicroprocessor can signal through opto-coupler 102 a confirmation toshut down power supply 10. If signaled by the microprocessor,opto-coupler 102 pulls state pin 48 to ground and the output ofcomparator 80 becomes a logic one signifying that the voltage on statepin 48 is below the reference voltage at node 71 of reference generator60. The output of logic circuit 86 transitions to a logic one valuecausing toggle flip-flop 88 to change states such that the signal MODEis a logic zero value and power supply 10 is off. The microprocessor“reads” each momentary closure of switch 108 by the light emitted fromLED 106. The state of toggle flip-flop 88 is changed in accordance withthe signal received by opto-coupler 102. Thus, the momentary closure ofswitch 108 allows the microprocessor to control when power supply 10 isturned on or turned off.

FIG. 5 is a schematic diagram of a brown-out interface circuit for usewith the state circuit of FIG. 1 in accordance with yet anotherembodiment of the present invention. This fourth operating mode includesusing brown-out interface circuit 112 (FIG. 5) with state circuit 50(FIG. 2) for controlling the operation of power supply 10 (FIG. 1).Briefly referring to FIG. 5, resistor 114 has a first terminal commonlyconnected to a first terminal of resistor 116 and to a terminal ofcapacitor 120, forming node 48C. Node 48C is connected to state pin 48of state circuit 50. A second terminal of resistor 114 is connected to apower supply conductor such as, for example, ground. The other terminalof capacitor 120 is connected to a power supply conductor which isoperating at a potential of, for example, ground. The second terminal ofresistor 116 is connected to an anode of Zener diode 118. A cathode ofZener diode 118 is connected to a voltage such as, for example, arectified line voltage.

In the fourth mode of operation, state circuit 50 is powered on and thesignal MODE is at a logic one value. The output of comparator 77 has alogic zero value indicating that the voltage on state pin 48 has a valueabove the reference voltage at node 67. The logic zero value at theinput of NAND gate 84 causes the signal MODE to have a logic one valueand power supply 10 (FIG. 1) to be on. Brown-out interface circuit 112(FIG. 5) detects either a brown-out or a black-out condition on the linevoltage received by full-wave bridge rectifier 12 (FIG. 1). A brown-outoccurs when the line voltage is below the predetermined rectifiedvoltage as set by Zener diode 118. A black-out occurs when the linevoltage is substantially zero volts. By way of example, Zener diode 118has a reverse bias voltage of about 80 volts. During either a brown-outor a black-out, about 80 volts is dropped across Zener diode 118. Theresistor values for resistors 114 and 116 are selected to cause thevoltage on state pin 48 to drop below the reference voltage at node 71of reference generator 60 during either a brown-out or a black-outcondition. The output of comparator 80 transitions to a logic one valueduring either a brown-out or black-out. The output of logic circuit 86transitions to a logic one value, causing toggle flip-flop 88 to changestates from a logic one value to a logic zero value, thereby turning offpower supply 10. When neither the brown-out nor the black-out conditionis present, pin 48 is pulled high. The output of comparator 77 is alogic zero value when the voltage at state pin 48 is above the referencevoltage at node 67. A logic one value at the input S of toggle flip-flop88 causes the signal MODE to be a logic one value, thereby turning offpower supply 10.

State circuit 50, interface circuits 92 and 100 have been described withreferences with respect to ground. It should be noted that logic instate circuit 50 and interface circuits 92 and 100 can be reconfiguredto function with respect to the reference voltage V_(cc). It should befurther noted that state circuit 50 can also be reconfigured to functionwith opposite polarity logic at state pin 48.

It should be noted that capacitors 98, 110, and 120 as described inFIGS. 3, 4, and 5 can be selected to assure that power supply 10 isinitially programmed in the off state when the line voltage is applied.On the other hand, power supply 10 can be programmed in the on statewhen the line voltage is applied by removing capacitors 98, 110, and120. It should be further noted that capacitors 98, 110, and 120 can beselected to provide noise immunity without affecting the initiallyprogrammed on/off state.

By now it should be appreciated that a structure and method have beenprovided for controlling the on/off status of a programmable powersupply. The integrated power supply controller is inexpensive andprovides a cost effective system solution for switching power suppliesby reducing the number of external components. It has further been shownthat additional functionality has been provided through amulti-functional input for controlling the on/off switching function ofa power supply.

1. A power conversion integrated circuit, comprising: a state circuithaving an output that supplies a mode signal, wherein the state circuitincludes a comparator having a first input coupled for receiving acontrol signal and a second input coupled for receiving a firstreference signal, and a memory circuit having a first input coupled toan output of the comparator for setting an output state of the memorycircuit according to a value of the control signal; and a controlcircuit coupled for receiving the mode signal that sets a mode ofoperation, where the control circuit is responsive to a feedback signalfor providing a pulse-width modulated control signal.
 2. The powerconversion integrated circuit of claim 1, wherein the comparatorincludes: a first comparator having a first input coupled for receivingthe control signal, a second input coupled for receiving the firstreference signal, and an output coupled to the first input of the memorycircuit; and a second comparator having a first input coupled forreceiving the control signal, a second input coupled for receiving asecond reference signal, and an output coupled to a second input of thememory circuit.
 3. The power conversion integrated circuit of claim 2,further including a resistor divider network for generating the firstreference signal at a first output and the second reference signal at asecond output.
 4. The power conversion integrated circuit of claim 3,wherein the resistor divider network includes: a first resistor havingfirst and second terminals, the first terminal of the first resistorcoupled to a first power supply conductor; a second resistor havingfirst and second terminals, the first terminal of the second resistorcoupled to the second terminal of the first resistor and serving as thefirst output of the resistor divider network; and a third resistorhaving first and second terminals, the first terminal of the thirdresistor coupled to the second terminal of the second resistor andserving as the second output of the resistor divider network, and thesecond terminal of the third resistor coupled to a second power supplyconductor.
 5. The power conversion integrated circuit of claim 4,further including a pulse filter having an input coupled to the outputof the second comparator and an output coupled to the second input ofthe memory circuit.
 6. The power conversion integrated circuit of claim1, wherein the memory circuit has at least one storage element forstoring an operating mode of the power conversion integrated circuit. 7.The power conversion integrated circuit of claim 1, further including areset circuit having an input coupled to a logic under voltage signaland an output coupled to the control signal.
 8. A semiconductor chiphaving at least four external electrical connections, comprising: aninternal regulator; a state circuit having an output coupled to acontrol input of the internal regulator; a first electrical connectionterminal for coupling an external ground reference to an internal groundreference of the internal regulator; a second electrical connectionterminal for providing a pulse-width modulated output signal from anoutput of the internal regulator; a third electrical connection terminalcoupled for receiving a feedback signal at an input of the internalregulator to control the pulse-width modulated output signal; and afourth electrical connection terminal coupled for receiving a controlsignal which is applied to the state circuit to set a mode of operationof the internal regulator.
 9. The semiconductor chip of claim 8, furthercomprising a fifth electrical connection terminal coupled for receivinga bias voltage which is applied to the state circuit and to the internalregulator.
 10. A programmable power supply, comprising: a transformerreceiving a rectified signal at a primary side of the transformer; astate circuit having an input and an output for setting a mode ofoperation of the programmable power supply, wherein the state circuitincludes, a comparator circuit having a first input coupled to the inputof the state circuit for receiving a control signal and a second inputcoupled for receiving a first reference signal, and a memory circuithaving a first input coupled to an output of the comparator for settingan output state of the memory circuit according to a value of thecontrol signal where the output state of the memory circuit controls themode of operation; a control circuit coupled for receiving the outputstate of the memory circuit and wherein the control circuit isresponsive to a feedback signal for providing a pulse-width modulatedcontrol signal; and a transistor having a control terminal for receivingthe pulse-width modulated control signal, a first conduction terminalcoupled to the primary side of the transformer, and a second conductionterminal coupled to ground.
 11. The programmable power supply of claim10, wherein the comparator circuit includes: a first comparator having afirst input coupled for receiving the control signal, a second inputcoupled for receiving the first reference signal, and an output coupledto the first input of the memory circuit; and a second comparator havinga first input coupled for receiving the control signal, a second inputcoupled for receiving a second reference signal, and an output coupledto a second input of the memory circuit.
 12. The programmable powersupply of claim 10, further including a resistor divider network forgenerating a first reference signal at a first output and a secondreference signal at a second output.
 13. The programmable power supplyof claim 12, wherein the resistor divider network includes: a firstresistor having first and second terminals, the first terminal of thefirst resistor coupled to a first power supply conductor; a secondresistor having first and second terminals, the first terminal of thesecond resistor coupled to the second terminal of the first resistor andserving as the first output of the resistor divider network; and a thirdresistor having first and second terminals, the first terminal of thethird resistor coupled to the second terminal of the second resistor andserving as the second output of the resistor divider network, and thesecond terminal of the third resistor coupled to a second power supplyconductor.
 14. A method for controlling a mode of operation of a powerconverter, comprising the steps of: controlling a pulse-width modulatedoutput signal of the power converter in response to a feedback signal;and setting a memory state according to a comparison between a controlsignal and a first reference signal where the memory state controls themode of operation of the power converter.
 15. The method of claim 14,further comprising the steps of: monitoring a signal at an input pin;and maintaining a same operating state when the input pin receives avoltage about midway between an operating potential and a groundreference.
 16. The method of claim 14, further comprising the steps ofrequesting an on-operating state when a power supply is off and an inputpin receives a voltage greater than a first reference voltage.
 17. Themethod of claim 14, further comprising the steps of requesting a togglecondition when a power supply is on and an input pin receives a voltagegreater than a first reference voltage.
 18. The method of claim 15,further comprising the steps of requesting that an output state betoggled when a power supply is on and an input pin receives a voltageless than a second reference voltage.
 19. The method of claim 14,further comprising the step of operating in an off-operating state whena brown-out occurs that includes receiving a signal that is proportionalto a line voltage that is less than a second reference voltage.
 20. Themethod of claim 14, further comprising the step of operating in anoff-operating state when a black-out occurs that includes receiving asignal that is proportional to a line voltage that is less than a secondreference voltage.
 21. A power supply regulator circuit, comprising: aterminal adapted for receiving a mode control signal having a latchablestate, wherein the latchable state of the mode control signal controlsan operational on-state or a non-operational off-state of the powersupply regulator circuit; and a pulse width modulated (PWM) regulatorcircuit having a first input coupled for receiving a feedback signal,and an output for providing a PWM switching signal in response to thefeedback signal, the PWM regulator circuit including, (a) a firstcomparator having an input coupled for receiving the mode controlsignal, and an output having first or second states depending on acomparison between the mode control signal and a first reference value,(b) a second comparator having an input coupled for receiving the modecontrol signal, and an output having first or second states depending ona comparison between the mode control signal and a second referencevalue different from the first reference value, and (c) a logic circuithaving a first input coupled to the output of the first comparator, asecond input coupled to the output of the second comparator, the logiccircuit decoding the outputs of the first and second comparators andsetting the PWM regulator circuit to the non-operational off-state toconserve energy for an extended period of time as determined by thelatchable state of the mode control signal, wherein the regulatorcircuit is provided in a monolithic integrated circuit package and theterminal is coupled to a pin of the monolithic integrated circuitpackage.
 22. The power supply regulator circuit of claim 21, furtherincluding a latching circuit having an output coupled to the terminalfor providing the mode control signal.
 23. The power supply regulatorcircuit of claim 21, further including a microprocessor having an outputcoupled to the terminal for providing the mode control signal.
 24. Thepower supply regulator circuit of claim 21, further including a detectorcircuit monitoring a condition of the power supply regulator circuit andhaving an output coupled to the terminal for providing the mode controlsignal.
 25. The power supply regulator circuit of claim 26, wherein thefirst state of the mode control signal holds the non-operationaloff-state of the regulator circuit to conserve energy for a period oftime as determined by the mode control signal.
 26. A power supplyregulator circuit, comprising: a terminal coupled for receiving a modecontrol signal which controls on-state and off-state of the power supplyregulator circuit; and a regulator circuit having a first input coupledfor receiving a feedback signal, and an output for providing apulse-width modulated switching signal in response to the feedbacksignal, the regulator circuit including, (a) a first comparator havingan input coupled for receiving the mode control signal, and an outputhaving first or second states depending on a comparison between the modecontrol signal and a first reference value, (b) a second comparatorhaving an input coupled for receiving the mode control signal, and anoutput having first or second states depending on a comparison betweenthe mode control signal and a second reference value different from thefirst reference value, and (c) a logic circuit having a first inputcoupled to the output of the first comparator, a second input coupled tothe output of the second comparator, the logic circuit decoding theoutputs of the first and second comparators and setting the regulatorcircuit to a non-operational off-state, wherein the regulator circuit isprovided in a monolithic integrated circuit package and the terminal iscoupled to a pin of the monolithic integrated circuit package.
 27. Thepower supply regulator circuit of claim 26, further including a latchingcircuit having an output coupled to the terminal for providing the modecontrol signal.
 28. A power supply regulator circuit, comprising: aterminal adapted for receiving a mode control signal which controls anon-state and off-state of the power supply regulator circuit; a firstcomparator having an input coupled to the terminal for receiving themode control signal, and an output having first or second statesdepending on a comparison between the mode control signal and a firstreference value; a second comparator having an input coupled forreceiving the mode control signal, and an output having first or secondstates depending on a comparison between the mode control signal and asecond reference value different from the first reference value; a logiccircuit having a first input coupled to the output of the firstcomparator, and a second input coupled to the output of the secondcomparator; and a control circuit having a first input coupled forreceiving a feedback signal, a second input coupled for receiving anoperating potential, an output for providing a switching signal inresponse to the feedback signal, and a control input coupled to anoutput of the logic circuit for setting the power supply regulatorcircuit to an operational state or non-operational state.
 29. The powersupply regulator circuit of claim 28, wherein the mode control signalholds the non-operational state of the control circuit to conserveenergy for a period of time as determined by the mode control signal.30. The power supply regulator circuit of claim 28, wherein the modecontrol signal has first, second, and third values.
 31. The power supplyregulator circuit of claim 28, wherein the control circuit remains inthe non-operational off-state while the mode control signal has a firststate.
 32. The power supply regulator circuit of claim 28, furtherincluding a latching circuit having an output coupled to the terminalfor providing the mode control signal.
 33. The power supply regulatorcircuit of claim 28, wherein the regulator circuit is provided in amonolithic integrated circuit package.
 34. A power supply regulatorcircuit, comprising: a multi-function terminal coupled for receiving amode control signal which controls a plurality of operational modes ofthe power supply regulator circuit; a regulator circuit having a firstinput coupled for receiving a feedback signal, a second input coupledfor receiving an operating potential, and an output for providing aswitching signal in response to the feedback signal; and a chip disablecircuit having an input coupled for receiving the mode control signal,the chip disable circuit including, (a) a first comparator having aninput coupled for receiving the mode control signal, and an outputhaving first or second states depending on a comparison between the modecontrol signal and a first reference value, (b) a second comparatorhaving an input coupled for receiving the mode control signal, and anoutput having first or second states depending on a comparison betweenthe mode control signal and a second reference value different from thefirst reference value, and (c) a logic circuit having a first inputcoupled to the output of the first comparator, a second input coupled tothe output of the second comparator, and an output coupled to a controlinput of the regulator circuit, wherein the logic circuit decodes outputstates of the first and second comparators to select an operational modeof the regulator circuit.
 35. The power supply regulator circuit ofclaim 34, wherein the regulator circuit is provided in a monolithicintegrated circuit package.
 36. The power supply regulator circuit ofclaim 34, wherein the mode control signal has first, second, and thirdvalues.
 37. The power supply regulator circuit of claim 34, wherein oneof the plurality of operational modes is a non-operational state. 38.The power supply regulator circuit of claim 37, wherein the mode controlsignal holds the non-operational state of the control circuit toconserve energy for a period of time as determined by the mode controlsignal.
 39. The power supply regulator circuit of claim 37, wherein thecontrol circuit remains in the non-operational off-state while the modecontrol signal has a first state.
 40. The power supply regulator circuitof claim 34, further including a latching circuit having an outputcoupled to the terminal for providing the mode control signal.
 41. Apower supply regulator circuit, comprising: a terminal adapted forreceiving an external disable control signal; a pulse width modulated(PWM) regulator circuit having a first input coupled for receiving afeedback signal, a second input coupled for receiving an operatingpotential, and an output for providing a switching signal in response tothe feedback signal; and a chip disable circuit having an input coupledfor receiving the external disable control signal for disablingoperation of the PWM control circuit in response to the external disablecontrol signal, the chip disable circuit including, (a) a firstcomparator having an input coupled for receiving the external disablecontrol signal, and an output having first or second states depending ona comparison between the external disable control signal and a firstreference value, (b) a second comparator having an input coupled forreceiving the external disable control signal, and an output havingfirst or second states depending on a comparison between the externaldisable control signal and a second reference value different from thefirst reference value, and (c) a logic circuit having a first inputcoupled to the output of the first comparator, a second input coupled tothe output of the second comparator, and an output coupled to a controlinput of the PWM regulator circuit; wherein the chip disable circuitsets the power supply regulator circuit to a non-operational state toconserve energy for an extended period of time as determined by theexternal disable control signal.
 42. The power supply regulator circuitof claim 41, wherein the regulator circuit is provided in a monolithicintegrated circuit package.
 43. The power supply regulator circuit ofclaim 41, wherein the mode control signal holds the non-operationalstate of the control circuit to conserve energy for a period of time asdetermined by the mode control signal.
 44. The power supply regulatorcircuit of claim 41, wherein the mode control signal has first, second,and third values.
 45. The power supply regulator circuit of claim 41,further including a latching circuit having an output coupled to theterminal for providing the mode control signal.
 46. A semiconductor diehaving at least four external connections, comprising: a firstelectrical connection terminal coupled for receiving a feedback signal;a second electrical connection terminal for providing a switchingsignal; a third electrical connection terminal coupled to an externalground reference; a fourth electrical connection terminal coupled forreceiving an external disable control signal; a switching regulatorcircuit having a first input coupled to the first electrical connectionterminal for receiving the feedback signal, a second input coupled forreceiving an operating potential, an output coupled to the secondelectrical connection terminal for providing the switching signal inresponse to the feedback signal, and an internal ground coupled to thethird electrical connection terminal; and a chip disable circuit havingan input coupled for receiving the external disable control signal fordisabling operation of the switching regulator circuit in response tothe external disable control signal, the chip disable circuit including,(a) a first comparator having an input coupled for receiving theexternal disable control signal, and an output having first or secondstates depending on a comparison between the external disable controlsignal and a first reference value, (b) a second comparator having aninput coupled for receiving the external disable control signal, and anoutput having first or second states depending on a comparison betweenthe external disable control signal and a second reference valuedifferent from the first reference value, and (c) a logic circuit havinga first input coupled to the output of the first comparator, a secondinput coupled to the output of the second comparator, and an outputcoupled to a control input of the switching regulator circuit to disableoperation of the semiconductor chip.
 47. The semiconductor die of claim46, wherein the external disable control signal holds a non-operationalstate of the switching regulator circuit to conserve energy for a periodof time as determined by the external disable control signal.
 48. Thesemiconductor die of claim 46, wherein the mode control signal hasfirst, second, and third values.
 49. The semiconductor die of claim 46,further including a latching circuit having an output coupled to theterminal for providing the mode control signal.
 50. A method ofcontrolling an operational state of a power conversion control circuit,comprising: receiving an operating potential to the power conversioncontrol circuit on a first terminal; regulating the power conversioncontrol circuit in response to a feedback signal; receiving an externaldisable control signal on a second terminal for selecting an on-state oran off-state of the power conversion control circuit; comparing theexternal disable control signal to first and second reference values;and setting the power conversion control circuit to a plurality ofoperational states depending on whether the external disable controlsignal is greater than the first reference value, or the externaldisable control signal is between the first and second reference values,or the external disable control signal is less than the second referencevalue.
 51. The method of claim 50, wherein one of the plurality ofoperational modes is a non-operational state.
 52. The method of claim51, wherein the mode control signal holds the non-operational state ofthe control circuit to conserve energy for a period of time asdetermined by the mode control signal.
 53. The method of claim 50,wherein the mode control signal has first, second, and third value.